EDDIE’s BUS

This is a quick and technical run-down of the bus architecture. It isn’t the final specification, but a background summary that affects the development of various components.

The intention with EDDIE’s various cards is that they are self contained systems-on-a-card. Any bus between them is intended to facilitate intercommunication between these systems. A look at the common microcontroller technologies suggested:

• SPI - Serial peripheral interface. Can be very fast, but is mostly point to point without multiple end-point select signals.

• I2C - slower, multi-drop and somewhat constrained by available address spaces.

• UART - Generally point to point unless designed with additional software protocols which then preclude common console connections to PC’s etc.

We nominated all three for different purposes and usages. During development a single CANbus channel (two wires) was allocated on the backplace as well:

1. SPI

SPI (Serial Peripheral Interface) usually employs a data signal from the bus master to each listener, a data out signal from each listener, a clock signal as well as a select signal. The data out signals cannot be simply joined together, nor can the listener know if it is the target of the select signal.

To make the SPI more useful, each SPI channel is accompanied by a four bit bus select (up to 16 cards). Each card slot can identify which slot it is in and gate the select signal into itself when the bus select addresses it. The listener data out will be tri-state unless the card is selected.

Two SPI busses with accompanying card selects for each are available.

2. I2C

Two I2C (Inter-Integrated circuit) channels are available. It will be a matter for the system configuration to determine which cards act as masters on either bus. Two busses gives the flexibility for two bus masters on separate channels within a system.

3. UART

Two UART (Serial) channels are allocated on the backplane. No special consideration is given to the source/destination scheme between cards at this time. The first UART pair is intended for console/bootstrap connection to a host PC. Potentially the second UART pair may be allocated as a RS-485 multidrop bus.

4. CANbus

Any card with CANbus drivers can use the allocated CAN signals (CANH/CANL). The first EDDIE CPU supports CAN.

5. ETHERNET

The bus does not support Ethernet. We have allowed two spare signal lines that may be allocated to single pair Ethernet in future.

At present, ETHERNET may be built into the primary CPU card. This card is mounted adjacent to the power supply card in the frame. An auxilliary connector between this card and the power card allows a dedicated SPI bus to be connected to the power card.

In this initial design, this auxilliary SPI port is used to interface an Ethernet controller. This controller is connected to a five port 10/100 Ethernet switch module hosted on the power supply card. This way Ethernet is supported for one CPU card.

BUS/System Power

The first system is powered from 24VDC. This is a very common voltage in industrial situations. For this first four slot version of EDDIE, the 24VDC is converted to an isolated 15W 3.3VDC logic power supply. This allows ~3W per card and 3W headroom including the Ethernet interface.

Isolated logic supplies are an important consideration. Electrical noise conducted from the wired interfacing to the outside world can be hard to control or eliminate. This noise is very disruptive to complex logic systems. Our best practice design requirement is to “disconnect” the logic from the noise using optical or digital isolators. This adds complexity to the design but increases its robustness significantly.

Each card interfaces to the bus at 3.3V logic levels. It interfaces to its I/O terminals through an isolation barrier. Power for the directly connected electronics is either 24VDC (available from the bus) or converted to another useful voltage (eg 5V) on each card.

On our first CPU card, the CANbus and one I2C channel are designed for external connected. Each of these are also isolated for the same reasons.

Finally, a single auxilliary signal from the CPU card can switch the incoming 24VDC supply to output terminals. This allows the CPU card to use its program to power cycle external peripherals with no extra hardware.

Next Time

Havine now discussed our requirements and ideas for the backplane bus, and in a previous post the mechanical thinking we can present some initial prototyping work in the next post.